1. Field of the Invention
The present invention relates to nonvolatile memory devices and methods of fabricating the same and, more particularly, to phase changeable memory cells and fabrication methods thereof.
2. Description of Related Art
Nonvolatile memory devices can retain stored data after their power supply is interrupted. Some nonvolatile memory devices use flash memory cells with stacked gate structures. Flash memory cells can include a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate electrode, which are sequentially stacked on a channel region. The reliability and the programming efficiency of flash memory cells can depend on the characteristics of the tunnel oxide layer and the coupling ratio of the cell.
A nonvolatile memory device that uses a phase changeable memory device instead of a flash memory device has been proposed. FIG. 1 illustrates an equivalent circuit of a phase changeable memory cell. Referring to FIG. 1, the phase changeable memory cell includes a single access transistor TA and a single variable resistor R, which are serially connected to each other. The variable resistor R serves as a data storage element, and includes a bottom electrode, a top electrode and a phase changeable material layer interposed therebetween. The top electrode of the variable resistor R is connected to a plate electrode PL. The access transistor TA includes a source region connected to the bottom electrode, a drain region spaced apart from the source region, and a gate electrode located over a channel region between the source and drain regions. The gate electrode and the drain region are electrically connected to a word line WL and a bit line BL, respectively. The equivalent circuit of the phase changeable memory cell is similar to that of a dynamic random access memory (DRAM) cell. However, the phase changeable memory cell is programmed in a much different fashion than a DRAM cell. For example, the phase changeable material layer transitions between two stable states based on temperature.
FIG. 2 is a graph that illustrates a property of the phase changeable material layer. In this graph, the abscissa represents time T and the ordinate represents temperature TMP of the phase changeable material layer.
Referring to FIG. 2, when the phase changeable material layer is heated to a temperature that is higher than its melting point Tm for a first time duration T1, and then cooled down rapidly, the phase changeable material layer is transformed into an amorphous state (refer to curve {circle around (1)}). In contrast, when the phase changeable material layer is heated to a temperature that is in a range between its crystallization temperature Tc and its melting temperature Tm for a second time duration T2 (longer than the first duration T1 ) and is then cooled down, the phase changeable material layer is transformed into a crystalline state (refer to curve {circle around (2)}). The resistivity of the phase changeable material layer in the amorphous state is higher than that of the phase changeable material layer in the crystalline state. Thus, information can be stored in the memory cell as a logic “1” or a logic “0” by setting the phase of the phase changeable material layer, and can be read by detecting the current that flows through the phase changeable material layer. A compound material layer containing germanium Ge, stibium Sb and tellurium Te (hereinafter, referred to a GST layer) can be used as the phase changeable material layer.
A method of fabricating the phase changeable memory device is described in U.S. Pat. No. 6,117,720 entitled “Method of making an integrated circuit electrode having a reduced contact area”.
FIG. 3 is a cross sectional view illustrating a variable resistor 30 described in the U.S. Pat. No. 6,117,720.
Referring to FIG. 3, a bottom electrode 10 is disposed over a semiconductor substrate (not shown). An interlayer insulation layer 12 having an opening is stacked on the bottom electrode 10. A lower portion of the opening is filled with a plug 14 that is electrically connected to the bottom electrode 10. A sidewall of the opening and an edge of the plug 14 are covered with a spacer 16. The remaining space of the opening is filled with a contact portion 18, and the contact portion 18 is electrically connected to the plug 14.
The contact portion 18 may be a phase changeable material layer or a conductive layer. When the contact portion 18 is a phase changeable material layer, the interlayer insulation layer 12 and the contact portion 18 are covered with a top electrode 20. When the contact portion 18 is a conductive layer, the contact portion 18 is covered with a phase changeable material layer pattern and the phase changeable material layer pattern is covered with a top electrode.
FIGS. 4 and 5 are enlarged sectional views of the contact portion 18 shown in FIG. 3. FIG. 4 illustrates a contact portion 18a that includes a phase transformation region 22, and FIG. 5 illustrates a contact portion 18b that is a conductive layer, and that is covered by a phase changeable material layer pattern 20 having a phase transformation region 22.